MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 286
![IC MPU 32BIT COLDF 90MHZ 208FQFP](/photos/12/43/124330/mcf5307ai90b_sml.jpg)
MCF5307AI90B
Manufacturer Part Number
MCF5307AI90B
Description
IC MPU 32BIT COLDF 90MHZ 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307AI90B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
90MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Maximum Clock Frequency
90 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
90MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
FQFP
Program Memory Size
8KB
Cpu Speed
90MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5307AI90B
Manufacturer:
FREESCAL
Quantity:
153
Company:
Part Number:
MCF5307AI90B
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCF5307AI90B
Manufacturer:
FREESCALE
Quantity:
20 000
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Reset
1
Address
DMA Controller Module Programming Model
DSR[DONE], shown in Figure 12-9, is set when the block transfer is complete.
When a transfer sequence is initiated and BCRn[BCR] is not divisible by 16, 4, or 2 when
the DMA is configured for line, longword, or word transfers, respectively, DSRn[CE] is set
and no transfer occurs. See Section 12.4.5, “DMA Status Registers (DSR0–DSR3).”
12.4.4 DMA Control Registers (DCR0–DCR3)
DCRn, Figure 12-8, is used for configuring the DMA controller module. Note that
DCR[AT] is available only if BCR24BIT = 1.
Table 12-3 describes DCR fields.
Field
Addr
R/W
31
30
12-8
Bits
Available only if BCR24BIT = 1, otherwise reserved.
Reset
Reset
Bit
Field INT EEXT
Field AT
R/W
R/W
15
INT
EEXT
Name
31
15
0
1
14
30
14
Interrupt on completion of transfer. Determines whether an interrupt is generated by completing a
transfer or by the occurrence of an error condition.
0 No interrupt is generated.
1 Internal interrupt signal is enabled.
Enable external request. Care should be taken because a collision can occur between the START
bit and DREQ when EEXT = 1.
0 External request is ignored.
1 Enables external request to initiate transfer. Internal request is always enabled. It is initiated by
writing a 1 to the START bit.
13
CS
29
Figure 12-8. DMA Control Registers (DCRn)
Freescale Semiconductor, Inc.
AA
28
12
Table 12-3. DCRn Field Descriptions
For More Information On This Product,
Figure 12-7. BCRn—BCR24BIT = 0
27
11
MBAR + 0x30C, 0x34C, 0x38C, 0x3AC
BWC
Go to: www.freescale.com
MBAR + 0x308, 0x348, 0x388, 0x3A8
MCF5307 User’s Manual
10
0000_0000_0000_0000
25
0000_0000_0000_0000
9
SAA S_RW SINC
24
BCR
R/W
R/W
8
Description
23
N/A
—
7
22
6
21
SSIZE
5
20
4
DINC
19
3
18
DSIZE
2
17
1
START
16
0
0
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