MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 253

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset
11.4.3 Synchronous Register Set
The memory map in Table 11-1 is the same for both synchronous and asynchronous
operation. However, some bits are different, as noted in the following sections.
11.4.3.1 DRAM Control Register (DCR) in Synchronous Mode
The DRAM control register (DCR), Figure 11-15, controls refresh logic.
Table 11-12 describes DCR fields.
Address/
A: Address and Data Timing with EDGESEL Tied High
Field
Addr
R/W
BCLKO
Bits
15
14
13
Data
SO
Name
15
0
NAM
SO
—
Figure 11-15. DRAM Control Register (DCR) (Synchronous Mode)
VALID
14
—
Synchronous operation. Selects synchronous or asynchronous mode. When in synchronous mode,
the DRAM controller can be switched to ADRAM mode only by resetting the MCF5307.
0 Asynchronous DRAMs. Default at reset.
1 Synchronous DRAMs
Reserved, should be cleared.
No address multiplexing. Some implementations require external multiplexing. For example, when
linear addressing is required, the DRAM should not multiplex addresses on DRAM accesses.
0 The DRAM controller multiplexes the external address bus to provide column addresses.
1 The DRAM controller does not multiplex the external address bus to provide column addresses.
Table 11-12. DCR Field Descriptions (Synchronous Mode)
Figure 11-14. Using EDGESEL to Change Signal Timing
NAM COC
13
VALID
Chapter 11. Synchronous/Asynchronous DRAM Controller Module
Address/
Buffered
C: Address and Data Timing with EDGESEL Tied to Buffered Clock
12
BCLKO
BCLKO
Freescale Semiconductor, Inc.
Data
For More Information On This Product,
VALID
11
IS
VALID
Go to: www.freescale.com
10
VALID
RTIM
Buffer Delay
9
VALID
MBAR + 0x100
8
Uninitialized
R/W
Description
Address/
B: Address and Data Timing with EDGESEL Tied Low
BCLKO
VALID
Data
7
6
VALID
VALID
5
RC
4
Synchronous Operation
VALID
3
VALID
2
1
11-19
0