MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 122

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Cache Management
4.11 Cache Management
The cache can be enabled and configured by using a MOVEC instruction to access CACR.
A hardware reset clears CACR, disabling the cache and removing all configuration
information; however, reset does not affect the tags, state information, and data in the cache.
Set CACR[CINVA] to invalidate the cache before enabling it.
The privileged CPUSHL instruction supports cache management by selectively pushing
and invalidating cache lines. The address register used with CPUSHL directly addresses the
cache’s directory array. The CPUSHL instruction flushes a cache line.
The value of CACR[DPI] determines whether CPUSHL invalidates a cache line after it is
pushed. To push the entire cache, implement a software loop to index through all sets and
through each of the four lines within each set (a total of 512 lines). The state of CACR[EC]
does not affect the operation of CPUSHL or CACR[CINVA]. Disabling the cache by setting
CACR[EC] makes the cache nonoperational without affecting tags, state information, or
contents.
The contents of An used with CPUSHL specify cache row and line indexes. This differs
from the MC68040 where a physical address is specified. Figure 4-10 shows the An format.
The following code example flushes the entire cache:
_cache_disable:
_cache_flush:
setloop:
4-24
31
nop
move.w
jsr
clr.l
movec
movec
move.l
movec
rts
nop
moveq.l
moveq.l
move.l
cpushl
add.l
addq.l
cmpi.l
bne
moveq.l
addq.l
0
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For More Information On This Product,
#0x2700,SR
_cache_flush
d0
d0,ACR0
d0,ACR1
#0x01000000,d0
d0,CACR
#0,d0
#0,d1
d0,a0
bc,(a0)
#0x0010,a0
#1,d1
#128,d1
setloop
#0,d1
#1,d0
Figure 4-10. An Format
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MCF5307 User’s Manual
11
10
;mask off IRQs
;flush the cache completely
;ACR0 off
;ACR1 off
;Invalidate and disable cache
;synchronize—flush store buffer
;initialize way counter
;initialize set counter
;initialize cpushl pointer
;push cache line a0
;increment set index by 1
;increment set counter
;are sets for this way done?
;set counter to zero again
;increment to next way
Set Index
4
3
Line Index
0