MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 338

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Operation
mode may still contain error detection and correction information. One way to provide error
detection, if 8-bit characters are not required, is to use software to calculate parity and
append it to the 5-, 6-, or 7-bit character.
14.5.5 Bus Operation
This section describes bus operation during read, write, and interrupt acknowledge cycles
to the UART module.
14.5.5.1 Read Cycles
The UART module responds to reads with byte data. Reserved registers return zeros.
14.5.5.2 Write Cycles
The UART module accepts write data as bytes. Write cycles to read-only or reserved
registers complete normally without exception processing, but data is ignored.
14.5.5.3 Interrupt Acknowledge Cycles
The UART module supplies the interrupt vector in response to a UART IACK cycle. If
UIVRn is not initialized to provide a vector number, a spurious exception is taken if an
interrupt is generated. This works in conjunction with the interrupt controller, which allows
a programmable priority level.
14.5.6 Programming
The software flowchart, Figure 14-27, consists of the following:
14-28
• UART module initialization—These routines consist of SINIT and CHCHK (sheets
• I/O driver routine—This routine (sheets 4 and 5) consists of INCH, the terminal
1 and 2). Before SINIT is called at system initialization, the calling routine allocates
2 words on the system stack. On return to the calling routine, SINIT passes UART
status data on the stack. If SINIT finds no errors, the transmitter and receiver are
enabled. SINIT calls CHCHK to perform the checks. When called, SINIT places the
UART in local loop-back mode and checks for the following errors:
— Transmitter never ready
— Receiver never ready
— Parity error
— Incorrect character received
input character routine which gets a character from the receiver, and OUTCH, which
sends a character to the transmitter.
The UART module is accessed by the CPU with zero wait
states, as BCLKO is used for the UART module.
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MCF5307 User’s Manual
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