MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 261

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.4.4.2 Interfacing Example
The tables in the previous section can be used to configure the interface in the following
example. To interface one 2M x 32-bit x 4 bank SDRAM component (8 columns) to the
MCF5307, the connections would be as shown in Table 11-31.
11.4.4.3 Burst Page Mode
SDRAM can efficiently provide data when an SDRAM page is opened. As soon as SCAS
is issued, the SDRAM accepts a new address and asserts SCAS every clock for as long as
accesses are in that page. In burst page mode, there are multiple read or write operations for
every
the associated SDRAM. The primary cycle of the transfer generates the
WRITE
the transfer completes, the
Note that in synchronous operation, burst mode and address incrementing during burst
cycles are controlled by the MCF5307 DRAM controller. Thus, instead of the SDRAM
enabling its internal burst incrementing capability, the MCF5307 controls this function.
This means that the burst function that is enabled in the mode register of SDRAMs must be
disabled when interfacing to the MCF5307.
Figure 11-18 shows a burst read operation. In this example, DACR[CASL] = 01, for an
SRAS-to-SCAS delay (t
MCF5307
Pins
Row
Column
SDRAM
Pins
MCF5307
Pins
Row
Column
SDRAM
Pins
Table 11-29. MCF5307 to SDRAM Interface (32-Bit Port, 11-Column Address Lines)
Table 11-30. MCF5307 to SDRAM Interface (32-Bit Port, 12-Column Address Lines)
SDRAM
Pins
MCF5307
Pins
ACTV
commands; secondary cycles generate only
A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31
A15 A14 A13 A12 A11 A10
15
A0
15
A0
2
2
command in the SDRAM if the requested transfer size exceeds the port size of
A0
A15
A1
14
A1
14
3
3
A14
A2
13
A1
4
13
A2
4
Chapter 11. Synchronous/Asynchronous DRAM Controller Module
Table 11-31. SDRAM Hardware Connections
A3
12
A13
5
A3
A2
12
Freescale Semiconductor, Inc.
5
RCD
For More Information On This Product,
A4
11
PALL
6
A4
A12
11
A3
6
) of 2 BCLKO cycles. Because t
A5
10
7
A5
10
A11
command is generated to prepare for the next access.
7
A4
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A6
9
8
A9
A6
9
8
A10
A5
A7
17
16
A17 A19 A21 A23 A25 A26 A27 A28 A29 A30 A31
A7
17
16
A6
A9
A8
19
18
A8
19
18
A17
A7
A9 A10 A11 A12 A13 A14 A15 A16 A17 A18
21
20
21
20
A9
READ
A18
23
22
A8
A10 A11 A12 A13 A14 A15 A16 A17
23
22
24
A19
or
A9
25
24
WRITE
RCD
25
A10 = CMD
26
is equal to the read CAS
26
A20
commands. As soon as
Synchronous Operation
27
27
ACTV
28
28
BA0
A21
and
29
29
READ
30
30
BA1
A22
11-27
31
31
or