MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 186

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programming Model
Table 6-3 describes RSR fields.
6.2.4 Software Watchdog Timer
The software watchdog timer prevents system lockup should the software become trapped
in loops with no controlled exit. The software watchdog timer can be enabled or disabled
through SYPCR[SWE]. If enabled, the watchdog timer requires the periodic execution of
a software watchdog servicing sequence. If this periodic servicing action does not occur,
the timer times out, resulting in a watchdog timer IRQ or hardware reset with RSTO driven
low, as programmed by SYPCR[SWRI].
If the timer times out and the software watchdog transfer acknowledge enable bit
(SYPCR[SWTA]) is set, a watchdog timer IRQ is asserted. Note that the software watchdog
timer IACK cycle cannot be autovectored.
If a software watchdog timer IACK cycle has not occurred after another timeout, SWT TA
is asserted in an attempt to terminate the bus cycle and allow the IACK cycle to proceed.
The setting of SYPCR[SWTAVAL] indicates that the watchdog timer TA was asserted.
Figure 6-4 shows termination of a locked bus.
6-6
Bits
4–0
7
6
5
SWTR
Name
HRST
—
—
Hardware or system reset
1 An external device driving RSTI caused the last reset. Assertion of reset by an external
Reserved, should be cleared.
Software watchdog timer reset
1 The last reset was caused by the software watchdog timer. If SYPCR[SWRI] = 1 and the
Reserved, should be cleared.
device causes the core processor to take a reset exception. All registers in internal
peripherals and the SIM are reset.
software watchdog timer times out, a hardware reset occurs.
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 6-3. RSR Field Descriptions
Go to: www.freescale.com
MCF5307 User’s Manual
Description