MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 316

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Descriptions
14.3.2 UART Mode Register 2 (UMR2n)
UART mode registers 2 (UMR2n) control UART module configuration. UMR2n can be
read or written when the mode register pointer points to it, which occurs after any access to
UMR1n. UMR2n accesses do not update the pointer.
Table 14-3 describes UMR2n fields.
Bits
7–6
14-6
Address
5
4
Reset
Field
R/W
TxRTS Transmitter ready-to-send. Controls negation of RTS to automatically terminate a message
TxCTS Transmitter clear-to-send. If both TxCTS and TxRTS are enabled, TxCTS controls the operation of the
Name
CM
Channel mode. Selects a channel mode. Section 14.5.3, “Looping Modes,” describes individual
modes.
00 Normal
01 Automatic echo
10 Local loop-back
11 Remote loop-back
transmission. Attempting to program a receiver and transmitter in the same channel for RTS control is
not permitted and disables RTS control for both.
0 The transmitter has no effect on RTS.
1 In applications where the transmitter is disabled after transmission completes, setting this bit
transmitter.
0 CTS has no effect on the transmitter.
1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to
7
automatically clears UOP[RTS] one bit time after any characters in the channel transmitter shift and
holding registers are completely sent, including the programmed number of stop bits.
send a character. If CTS is asserted, the character is sent; if it is negated, the channel TxD remains
in the high state and transmission is delayed until CTS is asserted. Changes in CTS as a character is
being sent do not affect its transmission.
CM
MBAR + 0x1C0, 0x200. After UMR1n is read or written, the pointer points to UMR2n.
Figure 14-3. UART Mode Register 2 (UMR2n)
6
Freescale Semiconductor, Inc.
Table 14-3. UMR2n Field Descriptions
For More Information On This Product,
TxRTS
5
Go to: www.freescale.com
MCF5307 User’s Manual
TxCTS
4
0000_0000
Description
R/W
3
SB
0