MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 29

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table
Number
17-10
17-11
17-12
17-13
17-14
17-15
17-16
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
18-12
19-1
19-2
19-3
19-4
20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
20-9
20-10
20-11
20-12
20-13
20-14
20-15
A-1
A-2
A-3
A-4
A-5
Data Pin Configuration ............................................................................................. 17-12
D7 Selection of CS0 Automatic Acknowledge ........................................................ 17-13
D6 and D5 Selection of CS0 Port Size ..................................................................... 17-13
D4/ADDR_CONFIG, Address Pin Assignment....................................................... 17-13
CLKIN Frequency .................................................................................................... 17-13
BCLKO/PSTCLK Divide Ratios.............................................................................. 17-14
Processor Status Signal Encodings ........................................................................... 17-19
ColdFire Bus Signal Summary ................................................................................... 18-1
Bus Cycle Size Encoding............................................................................................ 18-3
Accesses by Matches in CSCRs and DACRs ............................................................. 18-5
Bus Cycle States ......................................................................................................... 18-6
Allowable Line Access Patterns ............................................................................... 18-12
MCF5307 Arbitration Protocol States ...................................................................... 18-20
ColdFire Bus Arbitration Signal Summary............................................................... 18-21
Cycles for Basic No-Wait-State External Master Access......................................... 18-23
Cycles for External Master Burst Line Access to 32-Bit Port .................................. 18-24
MCF5307 Two-Wire Bus Arbitration Protocol Transition Conditions.................... 18-28
Three-Wire Bus Arbitration Protocol Transition Conditions ................................... 18-32
Data Pin Configuration ............................................................................................. 18-35
JTAG Pin Descriptions ............................................................................................... 19-3
JTAG Instructions....................................................................................................... 19-5
IDCODE Bit Assignments.......................................................................................... 19-6
Boundary-Scan Bit Definitions................................................................................... 19-7
Absolute Maximum Ratings ....................................................................................... 20-1
Operating Temperatures.............................................................................................. 20-1
DC Electrical Specifications ....................................................................................... 20-2
Clock Timing Specification ........................................................................................ 20-2
Input AC Timing Specification................................................................................... 20-3
Output AC Timing Specification ................................................................................ 20-4
Reset Timing Specification....................................................................................... 20-12
Debug AC Timing Specification .............................................................................. 20-12
Timer Module AC Timing Specification.................................................................. 20-14
I
I
UART Module AC Timing Specifications ............................................................... 20-16
General-Purpose I/O Port AC Timing Specifications............................................... 20-18
DMA AC Timing Specifications .............................................................................. 20-19
IEEE 1149.1 (JTAG) AC Timing Specifications ..................................................... 20-20
SIM Registers............................................................................................................... A-1
Interrupt Controller Registers ...................................................................................... A-1
Chip-Select Registers................................................................................................... A-2
DRAM Controller Registers ........................................................................................ A-3
General-Purpose Timer Registers ................................................................................ A-4
2
2
C Input Timing Specifications between SCL and SDA......................................... 20-15
C Output Timing Specifications between SCL and SDA ...................................... 20-15
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