MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 326

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset
Field
Addr
R/W
UART Module Signal Definitions
Table 14-12 describes UOP1 fields.
14.4 UART Module Signal Definitions
Figure 14-17 shows both the external and internal signal groups.
Figure 14-17. UART Block Diagram Showing External and Internal Interface Signals
An internal interrupt request signal (IRQ) is provided to notify the interrupt controller of an
interrupt condition. The output is the logical NOR of unmasked UISRn bits. The interrupt
level of a UART module is programmed in the interrupt controller in the system integration
module (SIM). The UART can use the autovector for the programmed interrupt level or
supply the vector from the UIVRn when the UART interrupt is acknowledged.
14-16
7–1
0
Bits
To Interrupt
Controller
Interface
—
RTS
to CPU
Name
External Clock (TIN)
(SIM)
7
Figure 14-16. UART Output Port Command Register (UOP1/UOP0)
BCLKO
Reserved, should be cleared.
Output port parallel output. Controls assertion (UOP1)/negation (UOP0) of RTS output.
0 Not affected.
1 Asserts RTS (UOP1). Negates RTS (UOP0).
UART0: MBAR + 0x1F8 (UOP1), 0x1FC (UOP0); UART1 0x238 (UOP1), 0x23C (UOP0)
or
Address Bus
Control
Table 14-12. UOP1/UOP0 Field Descriptions
Freescale Semiconductor, Inc.
For More Information On This Product,
Data
IRQ
Internal
Control
Logic
Go to: www.freescale.com
MCF5307 User’s Manual
—
UART Module
Internal Bus
0000_0000
Write only
Description
Four-Character
Transmit Buffer
Receive Buffer
Two-Character
Clock Source
Output Port
Generator
Input Port
RTS
CTS
RxD
TxD
1
External
Interface
Signals
RTS
0