MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 247

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 11-8 shows the write operation with the same configuration.
11.3.3.3 Continuous Page Mode
Continuous page mode (DACRn[PM] = 11) is a type of page mode that balances
performance, complexity, and size. In typical page-mode implementations, sequential
addresses are checked for multiple hits in a DRAM block. On a hit, RAS remains asserted
and CAS is asserted with the new column address. On a miss, RAS must be precharged
again before the bus cycle begins.
Continuous page mode supports page-mode operation without requiring an address holding
register per memory block and eliminates the delay for a miss-to-precharge RAS for the
upcoming bus cycle. Because the internal MCF5307 address bus is pipelined, addresses for
RAS[1] or [0]
RAS[1] or [0]
CAS[3:0]
DRAMW
CAS[3:0]
DRAMW
BCLKO
A[31:0]
D[31:0]
BCLKO
D[31:0]
A[31:0]
Figure 11-7. Burst Page-Mode Read Operation (4-3-3-3)
Figure 11-8. Burst Page-Mode Write Operation (4-3-3-3)
Row
Row
RCD = 0
RCD = 0
Chapter 11. Synchronous/Asynchronous DRAM Controller Module
Freescale Semiconductor, Inc.
Column
Column
For More Information On This Product,
CAS = 01
CAS = 01
Go to: www.freescale.com
Column
Column
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Asynchronous Operation
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11-13