MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 430

IC MPU 32BIT COLDF 90MHZ 208FQFP

MCF5307AI90B

Manufacturer Part Number
MCF5307AI90B
Description
IC MPU 32BIT COLDF 90MHZ 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets

Specifications of MCF5307AI90B

Core Processor
Coldfire V3
Core Size
32-Bit
Speed
90MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Maximum Clock Frequency
90 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
90MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
FQFP
Program Memory Size
8KB
Cpu Speed
90MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

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MCF5307AI90B
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JTAG Register Descriptions
The IEEE Standard 1149.1 requires the EXTEST, SAMPLE/PRELOAD, and BYPASS
instructions. IDCODE, CLAMP, and HIGHZ are optional standard instructions that the
MCF5307 implementation supports and are described in the IEEE Standard 1149.1.
19.4.2 IDCODE Register
The MCF5307 includes an IEEE Standard 1149.1-compliant JTAG identification register,
IDCODE, which is read by the MCF5307 JTAG instruction encoded as octal 1.
Table 19-3 describes IDCODE bit assignments.
Instruction
19-6
31–28
27–22
21–12
11–1
0
(0000 forH55J, 0001 for J20C)
BYPASS
31
CLAMP
Bits
(CMP)
(BYP)
Version Number
Version number. Indicates the revision number of the MCF5307
Design center. Indicates the ColdFire design center
Device number. Indicates an MCF5307
Indicates the reduced JEDEC ID for Motorola. Joint Electron Device Engineering Council (JEDEC)
Publication 106-A and Chapter 11 of the IEEE Standard 1149.1 give more information on this field.
Identifies this as the JTAG IDCODE register (and not the bypass register) according to the IEEE Standard
1149.1
30
Optional
Required
Class
29
110 Selects the bypass register and asserts functional reset while forcing all output and
111 Selects the single-bit bypass register, creating a single-bit shift register path from TDI
IR
Table 19-2. JTAG Instructions (Continued)
28
Freescale Semiconductor, Inc.
bidirectional pins configured as outputs to fixed, preloaded values in the
boundary-scan update registers. Enhances test efficiency by reducing the overall shift
path to one bit (the bypass register) while conducting an EXTEST type of instruction
through the boundary-scan register. CLAMP becomes active on the falling edge of
TCK in the Update-IR state when instruction-shift register data is equivalent to octal 6.
to the bypass register to TDO. Enhances test efficiency by reducing the overall shift
path when a device other than the MCF5307 is under test on a board design with
multiple chips on the overall 1149.1 defined boundary-scan chain. The bypass register
is implemented in accordance with 1149.1 so the shift register stage is set to logic 0
on the rising edge of TCK following entry into the capture-DR state. Therefore, the first
bit shifted out after selecting the bypass register is always a logic 0 (to differentiate a
part that supports an IDCODE register from a part that supports only the bypass
register).
BYPASS goes active on the falling edge of TCK in the Update-IR state when
instruction shift register data is equivalent to octal 7.
Table 19-3. IDCODE Bit Assignments
For More Information On This Product,
0 1 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 1
2
7
2
6
2
5
Go to: www.freescale.com
2
4
MCF5307 User’s Manual
2
3
2
2
2
1
2
0
Description
1
9
1
8
1
7
Description
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0

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