DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 976

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 930 of 1130
REJ09B0327-0400
DAS
MULXU
MULXS
DIVXU
DIVXS
CMP
NEG
EXTU
EXTS
TAS
DAS Rd
MULXU.B Rs,Rd
MULXU.W Rs,ERd
MULXS.B Rs,Rd
MULXS.W Rs,ERd
DIVXU.B Rs,Rd
DIVXU.W Rs,ERd
DIVXS.B Rs,Rd
DIVXS.W Rs,ERd
CMP.B #xx:8,Rd
CMP.B Rs,Rd
CMP.W #xx:16,Rd
CMP.W Rs,Rd
CMP.L #xx:32,ERd
CMP.L ERs,ERd
NEG.B Rd
NEG.W Rd
NEG.L ERd
EXTU.W Rd
EXTU.L ERd
EXTS.W Rd
EXTS.L ERd
TAS @ERd
Mnemonic
*3
W
W
W
W
W
W
W
W
W
B
B
B
B
B
B
B
B
B
L
L
L
L
L
2
4
6
Instruction Length (Bytes)
Addressing Mode and
2
2
2
4
4
2
2
4
4
2
2
2
2
2
2
2
2
2
2
4
Rd8 decimal adjust
Rd8 Rs8 Rd16 (unsigned
multiplication)
Rd16 Rs16 ERd32 (unsigned
multiplication)
Rd8 Rs8 Rd16 (signed
multiplication)
Rd16 Rs16 ERd32 (signed
multiplication)
Rd16÷Rs8 Rd16
(RdH: remainder, RdL: quotient)
(unsigned division)
ERd32÷Rs16 ERd32
(Ed: remainder, Rd: quotient)
(unsigned division)
Rd16÷Rs8 Rd16
(RdH: remainder, RdL: quotient)
(signed division)
ERd32÷Rs16 ERd32
(Ed: remainder, Rd: quotient)
(signed division)
Rd8-#xx:8
Rd8-Rs8
Rd16-#xx:16
Rd16-Rs16
ERd32-#xx:32
ERd32-ERs32
0-Rd8 Rd8
0-Rd16 Rd16
0-ERd32 ERd32
0
0
(<bit 7> of Rd16)
(<bits 15 to 8> of Rd16)
(<bit 15> of ERd32)
(<bits 31 to 16> of ERd32)
@ERd-0
(<bit 7> of @ERd)
(<bits 15 to 8> of Rd16)
(<bits 31 to 16> of ERd32)
CCR set, (1)
Operation
Rd8
—
— — —
— — —
— —
— —
— — [6]
— — [6]
— — [8]
— — [8]
—
—
— [3]
— [3]
— [4]
— [4]
—
—
—
— — 0
— — 0
— —
— —
— —
I
Condition Code
H N Z V C
*
—
—
[7]
[7]
[7]
[7]
—
—
—
—
—
—
—
—
*
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
States *
No. of
12
20
13
21
12
20
13
21
1
1
1
2
1
3
1
1
1
1
1
1
1
1
4
1