DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 556

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Section 16 I
When, with the I
must be checked in order to identify the source that set IRIC to 1. Although each source has a
corresponding flag, caution is needed at the end of a transfer.
When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set. The
IRTR flag (the DTC start request flag) is not set at the end of a data transfer up to detection of a
retransmission start condition or stop condition after a slave address (SVA) or general call address
match in I
Even when the IRIC flag and IRTR flag are set, the TDRE or RDRF internal flag may not be set.
The IRIC and IRTR flags are not cleared at the end of the specified number of transfers in
continuous transfer using the DTC. The TDRE or RDRF flag is cleared, however, since the
specified number of ICDR reads or writes have been completed.
Table 16.3 shows the relationship between the flags and the transfer states.
Table 16.3 Flags and Transfer States
MST TRS
1/0
1
1
1
1
0
0
0
0
0
0
0
0
Rev. 4.00 Sep 27, 2006 page 510 of 1130
REJ09B0327-0400
1/0
1
1
1/0
1/0
0
0
0
0
1/0
1/0
1
1/0
2
C bus format slave mode.
BBSY ESTP STOP IRTR AASX AL
0
0
1
1
1
1
1
1
1
1
1
1
0
2
C Bus Interface [Option]
2
C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags
0
0
0
0
0
0
0
0
0
0
0
0
1/0
0
0
0
0
0
0
0
0
0
0
0
0
1/0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1/0
0
0
1
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
AAS
0
0
0
0
0
1/0
1
1
0
0
0
0
0
ADZ
0
0
0
0
0
1/0
0
1
0
0
0
0
0
ACKB State
0
0
0
0/1
0/1
0
0
0
0
0/1
0
1
0/1
Idle state (flag clearing
required)
Start condition issuance
Start condition established
Master mode wait
Master mode transmit/
receive end
Arbitration lost
SAR match by first frame in
slave mode
General call address match
SARX match
Slave mode
transmit/receive end
(except after SARX match)
Slave mode
transmit/receive end (after
SARX match)
Stop condition detected