DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 478

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Section 15 Serial Communication Interface (SCI, IrDA)
Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode.
The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set the STOP
bit setting is invalid since stop bits are not added.
Bit 3
STOP
0
1
Notes: 1. In transmission, a single 1 bit (stop bit) is added to the end of a transmit character
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit
character.
Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format
is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in
asynchronous mode; it is invalid in synchronous mode.
For details of the multiprocessor communication function, see section 15.3.3, Multiprocessor
Communication Function.
Bit 2
MP
0
1
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the
baud rate generator. The clock source can be selected from , /4, /16, and /64, according to the
setting of bits CKS1 and CKS0.
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 15.2.8, Bit Rate Register (BRR).
Rev. 4.00 Sep 27, 2006 page 432 of 1130
REJ09B0327-0400
2. In transmission, two 1 bits (stop bits) are added to the end of a transmit character
before it is sent.
before it is sent.
Description
1 stop bit *
2 stop bits *
Description
Multiprocessor function disabled
Multiprocessor format selected
1
2
(Initial value)
(Initial value)