DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 639

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

18.2.6
STRn (n = 1 to 4) is an 8-bit register that indicates status information during host interface
processing. Bits 3, 1, and 0 are read-only bits to both the host and slave processors.
STR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 4 and Bit 2—Defined by User (DBU): The user can use these bits as necessary.
Bit 3—Command/Data (C/D D D D ): Receives the HA0 input when the host processor writes to IDR1,
and indicates whether IDR1 contains data or a command.
Bit 1—Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR1. This bit is an
internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads
IDR1.
The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For
details see table 18.7.
Bit 3
C/D D D D
0
1
Bit 1
IBF
0
1
Bit
Initial value
Slave Read/Write
Host Read/Write
Note: * Only 0 can be written, to clear the flag.
Status Register (STR)
Description
Contents of input data register (IDR1) are data
Contents of input data register (IDR1) are a command
Description
[Clearing condition]
When the slave processor reads IDR
[Setting condition]
When the host processor writes to IDR
DBU
R/W
R
7
0
DBU
R/W
R
6
0
DBU
R/W
R
5
0
DBU
R/W
R
4
0
Rev. 4.00 Sep 27, 2006 page 593 of 1130
C/D
R
R
3
0
DBU
R/W
R
Section 18 Host Interface
2
0
REJ09B0327-0400
IBF
R
R
1
0
(Initial value)
(Initial value)
R/(W) *
OBF
R
0
0