DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 538

IC H8S MCU FLASH 128K 100-QFP

DF2148ATE20

Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148ATE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 16 I
16.1.2
Figure 16.1 shows a block diagram of the I
Figure 16.2 shows an example of I/O pin connections to external circuits. Channel 0 I/O pins and
channel 1 I/O pins differ in structure, and have different specifications for permissible applied
voltages. For details, see section 26, Electrical Characteristics.
Rev. 4.00 Sep 27, 2006 page 492 of 1130
REJ09B0327-0400
Wait function in slave mode (I
A wait request can be generated by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait request is cleared when the next transfer becomes possible.
Three interrupt sources
Selection of 16 internal clocks (in master mode)
Direct bus drive (with SCL and SDA pins)
Automatic switching from formatless mode to I
Data transfer end (including transmission mode transition with I
reception after loss of master arbitration)
Address match: when any slave address matches or the general call address is received in
slave receive mode (I
Stop condition detection
Two pins—P52/SCL0 and P97/SDA0—(normally NMOS push-pull outputs) function as
NMOS open-drain outputs when the bus drive function is selected.
Two pins—P86/SCL1 and P42/SDA1—(normally CMOS pins) function as NMOS-only
outputs when the bus drive function is selected.
Formatless operation (no start/stop conditions, non-addressing mode) in slave mode
Operation using a common data pin (SDA) and independent clock pins (VSYNCI, SCL)
Automatic switching from formatless mode to I
Block Diagram
2
C Bus Interface [Option]
2
C bus format)
2
C bus format)
2
C bus interface.
2
C bus format (channel 0 only)
2
C bus format on the fall of the SCL pin
2
C bus format and address

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