DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 580

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Section 16 I
16.3.7
Setting the SW bit to 1 in DDCSWR enables formatless mode to be selected as the IIC0 operating
mode. Switching from formatless mode to the I
automatically when a falling edge is detected on the SCL pin.
The following four preconditions are necessary for this operation:
Automatic switching is performed from formatless mode to the I
DDCSWR is automatically cleared to 0 on detection of a falling edge on the SCL pin. Switching
from the I
DDCSWR to 1.
In formatless mode, bits (such as MSL and TRS) that control the I
must not be modified. When switching from the I
bit to 1 or clear it to 0 according to the transmit data (transmission or reception) in formatless
mode, then set the SW bit to 1. After automatic switching from formatless mode to the I
format (slave mode), in order to wait for slave address reception, the TRS bit is automatically
cleared to 0.
If a falling edge is detected on the SCL pin during formatless operation, the I
operating mode is switched to the I
detected.
Rev. 4.00 Sep 27, 2006 page 534 of 1130
REJ09B0327-0400
A common data pin (SDA) for formatless and I
Separate clock pins for formatless operation (VSYNCI) and I
A fixed 1 level for the SCL pin during formatless operation (the SCL pin does not output a low
level)
Settings of bits other than TRS in ICCR that allow I
Automatic Switching from Formatless Mode to I
2
C bus format to formatless mode is achieved by having software set the SW bit in
2
C Bus Interface [Option]
2
C bus format without waiting for a stop condition to be
2
C bus format (slave mode) is performed
2
C bus format to formatless mode, set the TRS
2
C bus format operation
2
C bus format operation
2
C Bus Format
2
2
C bus format when the SW bit in
C bus format operation (SCL)
2
C bus interface operating mode
2
C bus interface
2
C bus