DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 559

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

IRTR flag setting is performed when the TDRE or RDRF flag is set to 1. IRTR is cleared by
reading IRTR after it has been set to 1, then writing 0 in IRTR. IRTR is also cleared automatically
when the IRIC flag is cleared to 0.
Bit 4—Second Slave Address Recognition Flag (AASX): In I
this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in
SARX.
AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is
also cleared automatically when a start condition is detected.
Bit 5
IRTR
0
1
Bit 4
AASX
0
1
Description
Waiting for transfer, or transfer in progress
[Clearing conditions]
1. When 0 is written in IRTR after reading IRTR = 1
2. When the IRIC flag is cleared to 0
Continuous transfer state
[Setting conditions]
Description
Second slave address not recognized
[Clearing conditions]
1. When 0 is written in AASX after reading AASX = 1
2. When a start condition is detected
3. In master mode
Second slave address recognized
[Setting condition]
When the second slave address is detected in slave receive mode while FSX = 0
In I
When the TDRE or RDRF flag is set to 1 when AASX = 1
In other modes
When the TDRE or RDRF flag is set to 1
2
C bus interface slave mode
Rev. 4.00 Sep 27, 2006 page 513 of 1130
Section 16 I
2
C bus format slave receive mode,
2
C Bus Interface [Option]
REJ09B0327-0400
(Initial value)
(Initial value)