DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 37

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

15.3 Operation .......................................................................................................................... 453
15.4 SCI Interrupts.................................................................................................................... 486
15.5 Usage Notes ...................................................................................................................... 487
Section 16 I
16.1 Overview........................................................................................................................... 491
16.2 Register Descriptions ........................................................................................................ 496
16.3 Operation .......................................................................................................................... 521
16.4 Usage Notes ...................................................................................................................... 542
Section 17 Keyboard Buffer Controller
17.1 Overview........................................................................................................................... 559
15.3.1 Overview.............................................................................................................. 453
15.3.2 Operation in Asynchronous Mode ....................................................................... 455
15.3.3 Multiprocessor Communication Function............................................................ 466
15.3.4 Operation in Synchronous Mode ......................................................................... 474
15.3.5 IrDA Operation .................................................................................................... 483
16.1.1 Features................................................................................................................ 491
16.1.2 Block Diagram ..................................................................................................... 492
16.1.3 Input/Output Pins ................................................................................................. 494
16.1.4 Register Configuration......................................................................................... 495
16.2.1 I
16.2.2 Slave Address Register (SAR) ............................................................................. 499
16.2.3 Second Slave Address Register (SARX) ............................................................. 500
16.2.4 I
16.2.5 I
16.2.6 I
16.2.7 Serial/Timer Control Register (STCR) ................................................................ 516
16.2.8 DDC Switch Register (DDCSWR) ...................................................................... 518
16.2.9 Module Stop Control Register (MSTPCR) .......................................................... 520
16.3.1 I
16.3.2 Master Transmit Operation .................................................................................. 523
16.3.3 Master Receive Operation.................................................................................... 525
16.3.4 Slave Receive Operation...................................................................................... 528
16.3.5 Slave Transmit Operation .................................................................................... 531
16.3.6 IRIC Setting Timing and SCL Control ................................................................ 533
16.3.7 Automatic Switching from Formatless Mode to I
16.3.8 Operation Using the DTC .................................................................................... 535
16.3.9 Noise Canceler ..................................................................................................... 536
16.3.10 Sample Flowcharts............................................................................................... 536
16.3.11 Initialization of Internal State .............................................................................. 541
2
2
2
2
2
2
C Bus Data Register (ICDR) ............................................................................. 496
C Bus Mode Register (ICMR) ........................................................................... 501
C Bus Control Register (ICCR) ......................................................................... 504
C Bus Status Register (ICSR)............................................................................ 511
C Bus Data Format ............................................................................................ 521
C Bus Interface [Option]
........................................................................... 491
........................................................................ 559
Rev. 4.00 Sep 27, 2006 page xxxv of xliv
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C Bus Format ........................ 534