DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 584

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Section 16 I
Rev. 4.00 Sep 27, 2006 page 538 of 1130
REJ09B0327-0400
2
C Bus Interface [Option]
Figure 16.15 Flowchart for Master Receive Mode (Example)
No
No
No
No
Master receive operation
Set ACKB = 0 in ICSR
Set WAIT = 1 in ICMR
Set ACKB = 1 in ICSR
Set WAIT = 0 in ICMR
and SCP = 0 in ICCR
Set TRS = 0 in ICCR
Set TRS = 1 in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
Clear IRIC in ICCR
Write BBSY = 0
Last receive ?
Last receive ?
Read ICDR
Read ICDR
Read ICDR
IRIC = 1?
IRIC = 1?
IRIC = 1?
IRIC = 1?
End
Yes
No
Yes
Yes
No
Yes
Yes
Yes
[1] Select receive mode
[2] Start receiving. The first read is a dummy
[3] Wait for 1 byte to be received.
[4] Clear IRIC to trigger the 9th clock.
[5] Wait for 1 byte to be received.
[6] Read the receive data.
[7] Clear IRIC
[8] Wait for the next data to be received.
[9] Clear IRIC to trigger the 9th clock.
[10] Set ACKB = 1 so as to return no
[11] Clear IRIC to trigger the 9th clock.
[12] Wait for 1 byte to be received.
[13] Set WAIT = 0.
[14] Stop condition issuance.
read. After reading ICDR, please clear
IRIC immediately.
(8th clock falling edge)
(to end the wait insertion)
(9th clock risig edge)
(8th clock falling edge)
(to end the wait insertion)
acknowledge, or set TRS = 1 so as not
to issue extra clock.
(to end the wait insertion)
Read ICDR.
Clear IRIC.
(Note: After setting WAIT = 0, IRIC
should be cleared to 0.)