DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 427

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Bits 7 and 6—Input Synchronization Mode Select 1 and 0 (SIMOD1, SIMOD0): These bits
select the signal source of the IHI and IVI signals.
Bit 5—Synchronization Signal Connection Enable (SCONE): Selects the signal source of the
FRT FTI input and the TMR1 TMCI1/TMRI1 input.
Bit 4—Input Capture Start Bit (ICST): The TMRX external reset input (TMRIX) is connected
to the IHI signal. TMRX has input capture registers (TICR, TICRR, and TICRF). TICRR and
TICRF can measure the width of a short pulse by means of a single capture operation under the
control of the ICST bit. When a rising edge followed by a falling edge is detected on TMRIX after
the ICST bit is set to 1, the contents of TCNT at those points are captured into TICRR and TICRF,
respectively, and the ICST bit is cleared to 0.
Bit 7
SIMOD1
0
1
Bit 5
SCONE
0
1
Bit 4
ICST
0
1
Mode
Normal connection (Initial value) FTIA
Synchronization signal
connection mode
Bit 6
SIMOD0
0
1
0
1
Description
The TICRR and TICRF input capture functions are stopped
[Clearing condition]
When a rising edge followed by a falling edge is detected on TMRIX
The TICRR and TICRF input capture functions are operating
(Waiting for detection of a rising edge followed by a falling edge on TMRIX)
[Setting condition]
When 1 is written in ICST after reading ICST = 0
Mode
No signal
S-on-G mode
Composite mode
Separate mode
(Initial value)
FTIA
input
IVI
signal
Description
FTIB
FTIB
input
TMO1
signal
Rev. 4.00 Sep 27, 2006 page 381 of 1130
Description
FTIC
FTIC
input
VFBACKI
input
IHI Signal
HFBACKI input
CSYNCI input
HSYNCI input
HSYNCI input
Section 13 Timer Connection
FTID
FTID
input
IHI
signal
REJ09B0327-0400
VFBACKI input
IVI Signal
PDC input
PDC input
VSYNCI input
TMCI1 TMRI1
TMCI1
input
IHI
signal
(Initial value)
TMRI1
input
IVI
inverse
signal