DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 1062

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Appendix B Internal I/O Registers
ISR—IRQ Status Register
Rev. 4.00 Sep 27, 2006 page 1016 of 1130
REJ09B0327-0400
Bit
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flag.
Notes: n = 7 to 0
IRQ7 to IRQ0 flags
R/(W) *
0
1
IRQ7F
7
0
[Clearing conditions]
• Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF
• When interrupt exception handling is executed while low-level detection
• When IRQn interrupt exception handling is executed while falling, rising,
[Setting conditions]
• When IRQn input goes low when low-level detection is set
• When a falling edge occurs in IRQn input while falling edge detection is
• When a rising edge occurs in IRQn input while rising edge detection is
• When a falling or rising edge occurs in IRQn input while both-edge
is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high *
or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1) *
(IRQnSCB = IRQnSCA = 0)
set (IRQnSCB = 0, IRQnSCA = 1)
set (IRQnSCB = 1, IRQnSCA = 0)
detection is set (IRQnSCB = IRQnSCA = 1)
*
When a product, in which a DTC is incorporated, is used in the
following settings, the corresponding flag bit is not automatically
cleared even when exception handling, which is a clear condition, is
executed and the bit is held at 1.
(1) When DTCEA3 is set to 1 (ADI is set to an interrupt source),
(2) When DTCEA2 is set to 1 (ICIA is set to an interrupt source),
(3) When DTCEA1 is set to 1 (ICIB is set to an interrupt source),
(4) When DTCEA0 is set to 1 (OCIA is set to an interrupt souce),
When activation interrupt sources of DTC and IRQ interrupts are used
with the above combinations, clear the interrupt flag by software in the
interrupt handling routine of the corresponding IRQ.
R/(W) *
IRQ6F
6
0
IRQ4F flag is not automatically cleared.
IRQ5F flag is not automatically cleared.
IRQ6F flag is not automatically cleared.
IRQ7F flag is not automatically cleared.
R/(W) *
IRQ5F
5
0
R/(W) *
IRQ4F
4
0
H'FEEB
R/(W) *
IRQ3F
3
0
R/(W) *
IRQ2F
2
0
Interrupt Controller
R/(W) *
IRQ1F
1
0
R/(W) *
IRQ0F
0
0