DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 121

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

2.8.3
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address
(vector) from the exception vector table and branches to that address.
Types of Exception Handling and Their Priority
Exception handling is performed for resets, interrupts, and trap instructions. Table 2.7 indicates
the types of exception handling and their priority. Trap instruction exception handling is always
accepted in the program execution state.
Exception handling and the stack structure depend on the interrupt control mode set in SYSCR.
Table 2.7
Notes: 1. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,
Reset Exception Handling
After the RES pin has gone low and the reset state has been entered, when RES goes high again,
reset exception handling starts. When reset exception handling starts the CPU fetches a start
address (vector) from the exception vector table and starts program execution from that address.
All interrupts, including NMI, are disabled during reset exception handling and after it ends.
Priority
High
Low
2. Trap instruction exception handling is always accepted in the program execution state.
Exception-Handling State
or immediately after reset exception handling.
Type of Exception
Reset
Interrupt
Trap instruction
Exception Handling Types and Priority
Detection Timing
Synchronized with clock
End of instruction
execution or end of
exception-handling
sequence *
When TRAPA instruction
is executed
1
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Start of Exception Handling
Exception handling starts
immediately after a low-to-high
transition at the RES pin, or
when the watchdog timer
overflows.
When an interrupt is requested,
exception handling starts at the
end of the current instruction or
current exception-handling
sequence.
Exception handling starts when
a trap (TRAPA) instruction is
executed. *
2
REJ09B0327-0400
Section 2 CPU