DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 785

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

24.4
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock ( ).
24.5
The medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32
clocks.
24.6
The bus master clock selection circuit selects the system clock ( ) or one of the medium-speed
clocks ( /2, /4, /8, /16, or /32) to be supplied to the bus master, according to the settings of
bits SCK2 to SCK0 in SBYCR.
24.7
The subclock input circuit controls the subclock input from the EXCL pin.
Inputting the Subclock
When a subclock is used, a 32.768 kHz external clock should be input from the EXCL pin. In this
case, clear bit P96DDR to 0 in P9DDR and set bit EXCLE to 1 in LPWRCR.
The subclock input conditions are shown in table 24.6 and figure 24.8.
Table 24.6 Subclock Input Conditions
Item
Subclock input low pulse
width
Subclock input high pulse
width
Subclock input rise time
Subclock input fall time
Duty Adjustment Circuit
Bus Master Clock Selection Circuit
Medium-Speed Clock Divider
Subclock Input Circuit
Symbol
t
t
t
t
EXCLL
EXCLH
EXCLr
EXCLf
Min
—
—
—
—
V
CC
Typ
15.26
15.26
—
—
= 2.7 to 5.5 V
Rev. 4.00 Sep 27, 2006 page 739 of 1130
Max
—
—
10
10
Section 24 Clock Pulse Generator
Unit
µs
µs
ns
ns
Test Conditions
Figure 24.8
REJ09B0327-0400