DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 1128

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Appendix B Internal I/O Registers
TCONRI—Timer Connection Register I
Rev. 4.00 Sep 27, 2006 page 1082 of 1130
REJ09B0327-0400
Bit
Initial value
Read/Write
SIMOD1
Input synchronization mode select 1 and 0
SIMOD1
R/W
7
0
0
1
SIMOD0
SIMOD0
Synchronization signal connection enable
R/W
SCONE
6
0
0
1
0
1
0
1
Input capture start bit
0
1
SCONE
No signal
S-on-G mode
Composite mode
Separate mode
Normal
connection
Synchronization
signal connec-
tion mode
Input synchronization signal inversion
The TICRR and TICRF input capture functions are stopped
[Clearing condition]
When a rising edge followed by a falling edge is detected on TMRIX
The TICRR and TICRF input capture functions are operating
(Waiting for detection of a rising edge followed by a falling edge on TMRIX)
[Setting condition]
When 1 is written in ICST after reading ICST = 0
R/W
0
1
5
0
Input synchronization signal inversion
Mode
0
1
The HFBACKI pin state is used directly as the HFBACKI input
The HFBACKI pin state is inverted before use as the HFBACKI input
Mode
The VFBACKI pin state is used directly as the VFBACKI input
The VFBACKI pin state is inverted before use as the VFBACKI input
ICST
R/W
4
0
FTIA
input
IVI
signal
FTIA
Input synchronization signal inversion
HFBACKI input
CSYNCI input
HSYNCI input
HSYNCI input
0
1
HFINV
R/W
H'FFFC
The HSYNCI and CSYNCI pin states are used
directly as the HSYNCI and CSYNCI inputs
The HSYNCI and CSYNCI pin states are inverted
before use as the HSYNCI and CSYNCI inputs
3
0
FTIB
input
TMO1
signal
FTIB
IHI signal
VFINV
FTIC
input
VFBACKI
input
R/W
FTIC
2
0
VFBACKI input
PDC input
PDC input
VSYNCI input
Input synchronization
signal inversion
0
1
FTID
input
IHI
signal
HIINV
FTID
R/W
IVI signal
1
0
The VSYNCI pin state
is used directly as
the VSYNCI input
The VSYNCI pin state
is inverted before use
as the VSYNCI input
Timer Connection
TMCI1
TMCI1
input
IHI
signal
VIINV
R/W
0
0
TMRI1
TMRI1
input
IVI
inverse
signal