DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 534

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Section 15 Serial Communication Interface (SCI, IrDA)
Break Detection and Processing
When a framing error (FER) is detected, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the
parity error flag (PER) may also be set.
Note that, since the SCI continues the receive operation after receiving a break, even if the FER
flag is cleared to 0, it will be set to 1 again.
Sending a Break
The TxD pin has a dual function as an I/O port whose direction (input or output) is determined by
DR and DDR. This feature can be used to send a break.
Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced
by the value of DR (the pin does not function as the TxD pin until the TE bit is set to 1).
Consequently, DDR and DR for the port corresponding to the TxD pin should first be set to 1.
To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0.
When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission
state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin.
Receive Error Flags and Transmit Operations (Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission.
Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the transfer
rate.
In reception, the SCI samples the falling edge of the start bit using the base clock, and performs
internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the
base clock. This is illustrated in figure 15.23.
Rev. 4.00 Sep 27, 2006 page 488 of 1130
REJ09B0327-0400