DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 219
![IC H8S MCU FLASH 128K 100-QFP](/photos/28/61/286108/100-tqfp_sml.jpg)
DF2148ATE20
Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148ATE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20
HD64F2148ATE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.5
6.5.1
With this LSI, external space area 0 can be designated as burst ROM space, and burst ROM
interfacing can be performed.
External space can be designated as burst ROM space by means of the BRSTRM bit in BCR.
Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU
instruction fetches only. One or two states can be selected for burst access.
6.5.2
The number of states in the initial cycle (full access) of the burst ROM interface is in accordance
with the setting of the AST bit. Also, when the AST bit is set to 1, wait state insertion is possible.
One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in
BCR. Wait states cannot be inserted.
When the BRSTS0 bit in BCR is cleared to 0, burst access of up to 4 words is performed; when
the BRSTS0 bit is set to 1, burst access of up to 8 words is performed.
The basic access timing for burst ROM space is shown in figures 6.14 (a) and (b). The timing
shown in figure 6.14 (a) is for the case where the AST and BRSTS1 bits are both set to 1, and that
in figure 6.14 (b) is for the case where both these bits are cleared to 0.
Burst ROM Interface
Overview
Basic Timing
Rev. 4.00 Sep 27, 2006 page 173 of 1130
Section 6 Bus Controller
REJ09B0327-0400
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