DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 527

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

In serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with serial clock input or output.
2. The received data is stored in RSR in LSB-to-MSB order.
3. If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt
Figure 15.19 shows an example of SCI operation in reception.
Simultaneous Serial Data Transmission and Reception (Synchronous Mode): Figure 15.20
shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations.
Serial
clock
Serial
data
RDRF
ORER
After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be
transferred from RSR to RDR.
If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a
receive error is detected in the error check, the operation is as shown in table 15.11.
Neither transmit nor receive operations can be performed subsequently when a receive error
has been found in the error check.
(RXI) request is generated.
Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive-error
interrupt (ERI) request is generated.
RXI interrupt request
generated
Figure 15.19 Example of SCI Operation in Reception
Bit 7
RDR data read and
RDRF flag cleared to 0
in RXI interrupt handling
routine
Bit 0
1 frame
Section 15 Serial Communication Interface (SCI, IrDA)
Bit 7
Bit 0
RXI interrupt request
generated
Rev. 4.00 Sep 27, 2006 page 481 of 1130
Bit 1
ERI interrupt request
generated by overrun
error
Bit 6
REJ09B0327-0400
Bit 7