DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 461

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

read-only bit. It is set to 1 by an external reset, and when the RST/NMI bit is 1, is cleared to 0 by
an internal reset due to watchdog timer overflow.
14.2.4
The watchdog timer’s TCNT and TCSR registers differ from other registers in being more difficult
to write to. The procedures for writing to and reading these registers are given below.
Writing to TCNT and TCSR (Example of WDT0)
These registers must be written to by a word transfer instruction. They cannot be written to with
byte transfer instructions.
Figure 14.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the
same write address. For a write to TCNT, the upper byte of the written word must contain H'5A
and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written
word must contain H'A5 and the lower byte must contain the write data. This transfers the write
data from the lower byte to TCNT or TCSR.
Reading TCNT and TCSR (Example of WDT0)
These registers are read in the same way as other registers. The read addresses are H'FFA8 for
TCSR, and H'FFA9 for TCNT.
Bit 3
XRST
0
1
TCNT write
TCSR write
Figure 14.2 Format of Data Written to TCNT and TCSR (Example of WDT0)
Notes on Register Access
Address: H'FFA8
Address: H'FFA8
Description
Reset is generated by watchdog timer overflow
Reset is generated by external reset input
15
15
H'5A
H'A5
Rev. 4.00 Sep 27, 2006 page 415 of 1130
8 7
8 7
Section 14 Watchdog Timer (WDT)
Write data
Write data
REJ09B0327-0400
(Initial value)
0
0