DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 360

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Section 11 16-Bit Free-Running Timer
11.2.5
OCRDM is a 16-bit readable/writable register in which the upper 8 bits are fixed at H'00.
When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000,
the operation of ICRD is changed to include the use of OCRDM. The point at which input capture
D occurs is taken as the start of a mask interval. Next, twice the contents of OCRDM is added to
the contents of ICRD, and the result is compared with the FRC value. The point at which the
values match is taken as the end of the mask interval. New input capture D events are disabled
during the mask interval.
A mask interval is not generated when the ICRDMS bit is set to 1 and the contents of OCRDM are
H'0000.
OCRDM is initialized to H'0000 by a reset and in hardware standby mode.
11.2.6
TIER is an 8-bit readable/writable register that enables and disables interrupts.
TIER is initialized to H'01 by a reset and in hardware standby mode.
Bit 7—Input Capture Interrupt A Enable (ICIAE): Selects whether to request input capture
interrupt A (ICIA) when input capture flag A (ICFA) in TCSR is set to 1.
Rev. 4.00 Sep 27, 2006 page 314 of 1130
REJ09B0327-0400
Read/
Bit
Initial
Bit
Initial value
Read/Write
value
Write
Output Compare Register DM (OCRDM)
Timer Interrupt Enable Register (TIER)
15
R
0
14
ICIAE
R
0
R/W
7
0
13
R
0
ICIBE
12
R/W
R
0
6
0
11
R
0
ICICE
R/W
10
R
0
5
0
R
9
0
ICIDE
R/W
4
0
R
8
0
R/W
7
0
OCIAE
R/W
3
0
R/W
6
0
R/W
5
0
OCIBE
R/W
2
0
R/W
4
0
R/W
3
0
OVIE
R/W
1
0
R/W
2
0
R/W
1
0
—
—
0
1
R/W
0
0