DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 756

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Section 23 ROM
Rev. 4.00 Sep 27, 2006 page 710 of 1130
REJ09B0327-0400
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even
Note: Use a (z3) s write pulse for additional
Note 7: Write Pulse Width
Number of Writes n
Write pulse application subroutine
Wait (z1) s, (z2) s or (z3) s
programming.
2. Verify data is read in 16-bit (word) units.
3. Even bits for which programming has been completed in the 128-byte programming loop will be subjected to additional programming if they fail the subsequent
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional program data must be provided in
5. The write pulse of (z1) s or (z2) s is applied according to the progress of the programming operation. See Note 7 for the pulse widths. When writing of additional
6. See section 26.2.6, Flash Memory Characteristics, for the values of x, y, z1, z2, z3, , , , , , , and N.
Clear PSU bit in FLMCR2
1000
998
999
Program Data Computation Chart
Additional Program Data Computation Chart
Set PSU bit in FLMCR1
Sub-routine write pulse
Clear P bit in FLMCR1
10
11
12
13
storage area (128 kbytes)
Reprogram Data (X')
1
2
3
4
5
6
7
8
9
. .
.
Additional program data
Set P bit in FLMCR1
Reprogram data storage
if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
verify operation.
RAM. The reprogram and additional program data contents are modified as programming proceeds.
program data is executed, a (z3) µs write pulse should be applied. Reprogram data X means reprogram data when the write pulse is applied.
Original Data (D)
Program data storage
Disable WDT
Enable WDT
area (128 bytes)
area (128 bytes)
Wait (y) s
Wait ( ) s
Wait ( ) s
End sub
0
1
0
1
RAM
Write Time (z *
(H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
z2
z2
z2
. .
.
Figure 23.12 Program/Program-Verify Flowchart
Verify Data (V)
Verify Data (V)
6
) sec
Increment address
0
1
0
1
0
1
0
1
*6
*5
*6
*6
Additional Program Data (Y)
Reprogram Data (X)
Write 128-byte data in additional program data
Transfer reprogram data to reprogram data area *4
Store 128-byte program data in program
area in RAM consecutively to flash memory
NG
Write 128-byte data in RAM reprogram data
data area and reprogram data area
Additional program data computation
H'FF dummy write to verify address
1
0
1
1
0
1
1
1
Transfer additional program data
area consecutively to flash memory
to additional program data area
Reprogram data computation
Additional write pulse (z3) s
Clear SWE bit in FLMCR1
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set PV bit in FLMCR1
Start of programming
End of programming
Read verify data
(z1) s or (z2) s
data verification?
End of 128-byte
Program data =
Wait ( ) s
Wait (x) s
Wait ( ) s
Wait ( ) s
Write pulse
Wait ( ) s
verify data?
OK
OK
OK
m = 0?
m = 0
6
n = 1
6
Start
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Additional programming executed
Additional programming not executed
Additional programming not executed
n?
OK
n?
OK
Sub-routine-call
Comments
Comments
NG
NG
NG
NG
*6
*6
*4
*1
See Note 7 for pulse width
*6
*6
*6
*2
*4
*3
*6
*1
*6
m = 1
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Clear SWE bit in FLMCR1
Programming failure
Wait ( ) s
n
1000?
OK
NG
n
n + 1
*6