DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 484

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Section 15 Serial Communication Interface (SCI, IrDA)
Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception,
causing abnormal termination.
Bit 5
ORER
0
1
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is
Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in
asynchronous mode, causing abnormal termination.
Bit 4
FER
0
1
Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is
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REJ09B0327-0400
2. The receive data prior to the overrun error is retained in RDR, and the data received
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit
cleared to 0.
subsequently is lost. Also, subsequent serial reception cannot be continued while the
ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued,
either.
cleared to 0.
is not checked. If a framing error occurs, the receive data is transferred to RDR but the
RDRF flag is not set. Also, subsequent serial reception cannot be continued while the
FER flag is set to 1. In synchronous mode, serial transmission cannot be continued,
either.
Description
[Clearing condition]
When 0 is written in ORER after reading ORER = 1
[Setting condition]
When the next serial reception is completed while RDRF = 1 *
Description
[Clearing condition]
When 0 is written in FER after reading FER = 1
[Setting condition]
When the SCI checks the stop bit at the end of the receive data when reception ends,
and the stop bit is 0 *
2
2
(Initial value) *
(Initial value) *
1
1