DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 35

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

12.4 Interrupt Sources............................................................................................................... 369
12.5 8-Bit Timer Application Example..................................................................................... 370
12.6 Usage Notes ...................................................................................................................... 371
Section 13 Timer Connection
13.1 Overview........................................................................................................................... 377
13.2 Register Descriptions ........................................................................................................ 380
13.3 Operation .......................................................................................................................... 391
Section 14 Watchdog Timer (WDT)
14.1 Overview........................................................................................................................... 407
12.3.2 Compare-Match Timing....................................................................................... 363
12.3.3 TCNT External Reset Timing .............................................................................. 364
12.3.4 Timing of Overflow Flag (OVF) Setting ............................................................. 365
12.3.5 Operation with Cascaded Connection.................................................................. 365
12.3.6 Input Capture Operation ...................................................................................... 367
12.6.1 Contention between TCNT Write and Clear........................................................ 371
12.6.2 Contention between TCNT Write and Increment ................................................ 372
12.6.3 Contention between TCOR Write and Compare-Match ...................................... 373
12.6.4 Contention between Compare-Matches A and B................................................. 374
12.6.5 Switching of Internal Clocks and TCNT Operation............................................. 374
13.1.1 Features................................................................................................................ 377
13.1.2 Block Diagram ..................................................................................................... 377
13.1.3 Input and Output Pins .......................................................................................... 379
13.1.4 Register Configuration......................................................................................... 380
13.2.1 Timer Connection Register I (TCONRI) ............................................................. 380
13.2.2 Timer Connection Register O (TCONRO) .......................................................... 383
13.2.3 Timer Connection Register S (TCONRS)............................................................ 385
13.2.4 Edge Sense Register (SEDGR) ............................................................................ 387
13.2.5 Module Stop Control Register (MSTPCR) .......................................................... 390
13.3.1 PWM Decoding (PDC Signal Generation) .......................................................... 391
13.3.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) ..................... 393
13.3.3 Measurement of 8-Bit Timer Divided Waveform Period .................................... 394
13.3.4 IHI Signal and 2fH Modification ......................................................................... 396
13.3.5 IVI Signal Fall Modification and IHI Synchronization ....................................... 398
13.3.6 Internal Synchronization Signal Generation
13.3.7 HSYNCO Output ................................................................................................. 403
13.3.8 VSYNCO Output ................................................................................................. 404
13.3.9 CBLANK Output ................................................................................................. 405
14.1.1 Features................................................................................................................ 407
(IHG/IVG/CL4 Signal Generation) ..................................................................... 400
........................................................................................... 377
.............................................................................. 407
Rev. 4.00 Sep 27, 2006 page xxxiii of xliv