DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 30

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Section 6 Bus Controller
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Section 7 Data Transfer Controller (DTC)
7.1
7.2
Rev. 4.00 Sep 27, 2006 page xxviii of xliv
Overview........................................................................................................................... 151
6.1.1
6.1.2
6.1.3
6.1.4
Register Descriptions ........................................................................................................ 154
6.2.1
6.2.2
Overview of Bus Control .................................................................................................. 157
6.3.1
6.3.2
6.3.3
6.3.4
Basic Bus Interface ........................................................................................................... 160
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
Burst ROM Interface......................................................................................................... 173
6.5.1
6.5.2
6.5.3
Idle Cycle .......................................................................................................................... 175
6.6.1
6.6.2
Bus Arbitration.................................................................................................................. 177
6.7.1
6.7.2
6.7.3
Overview........................................................................................................................... 179
7.1.1
7.1.2
7.1.3
Register Descriptions ........................................................................................................ 182
7.2.1
7.2.2
7.2.3
Features................................................................................................................ 151
Block Diagram ..................................................................................................... 152
Pin Configuration................................................................................................. 153
Register Configuration......................................................................................... 153
Bus Control Register (BCR) ................................................................................ 154
Wait State Control Register (WSCR) .................................................................. 155
Bus Specifications................................................................................................ 157
Advanced Mode................................................................................................... 158
Normal Mode....................................................................................................... 158
I/O Select Signal .................................................................................................. 159
Overview.............................................................................................................. 160
Data Size and Data Alignment............................................................................. 160
Valid Strobes........................................................................................................ 162
Basic Timing........................................................................................................ 163
Wait Control ........................................................................................................ 171
Overview.............................................................................................................. 173
Basic Timing........................................................................................................ 173
Wait Control ........................................................................................................ 175
Operation ............................................................................................................. 175
Pin States in Idle Cycle ........................................................................................ 176
Overview.............................................................................................................. 177
Operation ............................................................................................................. 177
Bus Transfer Timing ............................................................................................ 178
Features................................................................................................................ 179
Block Diagram ..................................................................................................... 180
Register Configuration......................................................................................... 181
DTC Mode Register A (MRA) ............................................................................ 182
DTC Mode Register B (MRB)............................................................................. 184
DTC Source Address Register (SAR).................................................................. 185
................................................................................................... 151
................................................................... 179