LM3S600-IQN20-A0T Bookham Technology, Inc., LM3S600-IQN20-A0T Datasheet - Page 83

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LM3S600-IQN20-A0T

Manufacturer Part Number
LM3S600-IQN20-A0T
Description
Microcontroller
Manufacturer
Bookham Technology, Inc.
Datasheet
Device Capabilities 4 (DC4)
Base 0x400F.E000
Offset 0x01C
Type RO, reset 0x0000.001F
October 01, 2007
Reset
Reset
Type
Type
Bit/Field
31:5
4
3
2
1
0
RO
RO
31
15
0
0
Register 18: Device Capabilities 4 (DC4), offset 0x01C
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of GPIOs in the specific device. The format of this register is
consistent with the RCGC2, SCGC2, and DCGC2 clock control registers and the SRCR2 software
reset control register.
RO
RO
30
14
0
0
reserved
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
Type
27
11
0
0
RO
RO
RO
RO
RO
RO
reserved
RO
RO
26
10
0
0
Reset
0
1
1
1
1
1
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Port E Present
When set, indicates that GPIO Port E is present.
GPIO Port D Present
When set, indicates that GPIO Port D is present.
GPIO Port C Present
When set, indicates that GPIO Port C is present.
GPIO Port B Present
When set, indicates that GPIO Port B is present.
GPIO Port A Present
When set, indicates that GPIO Port A is present.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
GPIOE
RO
RO
20
0
4
1
GPIOD
LM3S600 Microcontroller
RO
RO
19
0
3
1
GPIOC
RO
RO
18
0
2
1
GPIOB
RO
RO
17
0
1
1
GPIOA
RO
RO
16
0
0
1
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