LM3S600-IQN20-A0T Bookham Technology, Inc., LM3S600-IQN20-A0T Datasheet - Page 34

• Manufacturer Part Number: LM3S600-IQN20-A0T
• Description: Microcontroller
• Manufacturer: Bookham Technology, Inc.

Memory Map
3
Table 3-1. Memory Map
34
Start
Memory
0x0000.0000
0x2000.0000
0x2010.0000
0x2200.0000
0x2204.0000
FiRM Peripherals
0x4000.0000
0x4000.4000
0x4000.5000
0x4000.6000
0x4000.7000
0x4000.8000
0x4000.C000
0x4000.D000
Peripherals
0x4002.0000
0x4002.0800
0x4002.4000
0x4003.0000
0x4003.1000
0x4003.2000
0x4003.C000
0x400F.D000
0x400F.E000
0x4200.0000
Private Peripheral Bus
Memory Map
The memory map for the LM3S600 controller is provided in Table 3-1 on page 34.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
Important:
In Table 3-1 on page 34, addresses not listed are reserved.
a
End
0x0000.7FFF
0x2000.1FFF
0x200F.FFFF
0x22003.FFFF
0x23FF.FFFF
0x4000.0FFF
0x4000.4FFF
0x4000.5FFF
0x4000.6FFF
0x4000.7FFF
0x4000.8FFF
0x4000.CFFF
0x4000.DFFF
0x4002.07FF
0x4002.0FFF
0x4002.7FFF
0x4003.0FFF
0x4003.1FFF
0x4003.2FFF
0x4003.CFFF
0x400F.DFFF
0x400F.FFFF
0x43FF.FFFF
Description
On-chip flash
Bit-banded on-chip SRAM
Reserved
Bit-band alias of 0x2000.0000 through 0x200F.FFFF
Reserved
Watchdog timer
GPIO Port A
GPIO Port B
GPIO Port C
GPIO Port D
SSI0
UART0
UART1
I2C Master 0
I2C Slave 0
GPIO Port E
Timer0
Timer1
Timer2
Analog Comparators
Flash control
System control
Bit-banded alias of 0x4000.0000 through 0x400F.FFFF
Preliminary
b
c
October 01, 2007
For details on
registers, see
page ...
108
108
-
103
-
195
125
125
125
125
265
222
222
304
317
125
168
168
168
326
108
56
-