LM3S600-IQN20-A0T Bookham Technology, Inc., LM3S600-IQN20-A0T Datasheet - Page 231

• Manufacturer Part Number: LM3S600-IQN20-A0T
• Description: Microcontroller
• Manufacturer: Bookham Technology, Inc.

UART Line Control (UARTLCRH)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x02C
Type R/W, reset 0x0000.0000
October 01, 2007
Reset
Reset
Type
Type
Bit/Field
31:8
6:5
7
4
RO
RO
31
15
0
0
Register 6: UART Line Control (UARTLCRH), offset 0x02C
The UARTLCRH register is the line control register. Serial parameters such as data length, parity,
and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register
must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH
register.
RO
RO
30
14
0
0
reserved
WLEN
Name
SPS
FEN
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
RO
RO
Type
27
11
R/W
R/W
R/W
0
0
RO
RO
RO
26
10
0
0
Reset
0
0
0
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Stick Parity Select
When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted
and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the
parity bit is transmitted and checked as a 1.
When this bit is cleared, stick parity is disabled.
UART Word Length
The bits indicate the number of data bits transmitted or received in a
frame as follows:
UART Enable FIFOs
If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO
mode).
When cleared to 0, FIFOs are disabled (Character mode). The FIFOs
become 1-byte-deep holding registers.
RO
RO
Value
24
0
8
0
0x3
0x2
0x1
0x0
reserved
Description
8 bits
7 bits
6 bits
5 bits (default)
SPS
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
WLEN
R/W
RO
21
0
5
0
FEN
R/W
RO
20
0
4
0
STP2
LM3S600 Microcontroller
R/W
RO
19
0
3
0
EPS
R/W
RO
18
0
2
0
PEN
R/W
RO
17
0
1
0
BRK
R/W
RO
16
0
0
0
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