LM3S600-IQN20-A0T Bookham Technology, Inc., LM3S600-IQN20-A0T Datasheet - Page 193
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LM3S600-IQN20-A0T
Manufacturer Part Number
LM3S600-IQN20-A0T
Description
Microcontroller
Manufacturer
Bookham Technology, Inc.
Datasheet
1.LM3S600-IQN20-A0T.pdf
(378 pages)
- Current page: 193 of 378
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10
10.1
10.2
October 01, 2007
Watchdog Timer
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or due to the failure of an external device to respond in the expected way.
The Stellaris
register, interrupt generation logic, a locking register, and user-enabled stalling.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
Block Diagram
Figure 10-1. WDT Module Block Diagram
Functional Description
The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches
the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt.
After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the
System Clock
Interrupt
®
Watchdog Timer module consists of a 32-bit down counter, a programmable load
Control / Clock /
Generation
WDTLOCK
WDTTEST
Interrupt
WDTCTL
WDTMIS
WDTICR
WDTRIS
WDTPCellID0
WDTPCellID1
WDTPCellID2
WDTPCellID3
Preliminary
Identification Registers
WDTPeriphID0
WDTPeriphID1
WDTPeriphID2
WDTPeriphID3
0x00000000
WDTPeriphID4
WDTPeriphID5
WDTPeriphID6
WDTPeriphID7
32-Bit Down
Comparator
WDTLOAD
Counter
LM3S600 Microcontroller
WDTVALUE
193
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