LM3S600-IQN20-A0T Bookham Technology, Inc., LM3S600-IQN20-A0T Datasheet - Page 64

• Manufacturer Part Number: LM3S600-IQN20-A0T
• Description: Microcontroller
• Manufacturer: Bookham Technology, Inc.

System Control
Masked Interrupt Status and Clear (MISC)
Base 0x400F.E000
Offset 0x058
Type R/W1C, reset 0x0000.0000
64
Reset
Reset
Type
Type
Bit/Field
31:7
6
5
4
3
2
1
0
RO
RO
31
15
0
0
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058
Central location for system control result of RIS AND IMC to generate an interrupt to the controller.
All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS
register (see page 61).
RO
RO
30
14
0
0
PLLLMIS
reserved
MOFMIS
BORMIS
reserved
LDOMIS
IOFMIS
CLMIS
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
RO
RO
Type
27
11
0
0
RO
RO
RO
RO
26
10
0
0
Reset
0
0
0
0
0
0
0
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL Lock Masked Interrupt Status
This bit is set when the PLL T
by writing a 1 to this bit.
Current Limit Masked Interrupt Status
This bit is set if the LDO’s CLE output asserts. The interrupt is cleared
by writing a 1 to this bit.
Internal Oscillator Fault Masked Interrupt Status
This bit is set if an internal oscillator fault is detected. The interrupt is
cleared by writing a 1 to this bit.
Main Oscillator Fault Masked Interrupt Status
This bit is set if a main oscillator fault is detected. The interrupt is cleared
by writing a 1 to this bit.
LDO Power Unregulated Masked Interrupt Status
This bit is set if LDO power is unregulated. The interrupt is cleared by
writing a 1 to this bit.
BOR Masked Interrupt Status
This bit is the masked interrupt status for any brown-out conditions. If
set, a brown-out condition was detected. An interrupt is reported if the
BORIM bit in the IMC register is set and the BORIOR bit in the PBORCTL
register is cleared. The interrupt is cleared by writing a 1 to this bit.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
PLLLMIS
R/W1C
RO
22
0
6
0
R/W1C
CLMIS
RO
21
0
5
0
READY
IOFMIS
R/W1C
RO
20
0
4
0
timer asserts. The interrupt is cleared
MOFMIS
R/W1C
RO
19
0
3
0
LDOMIS
R/W1C
RO
18
0
2
0
October 01, 2007
BORMIS
R/W1C
RO
17
0
1
0
reserved
RO
RO
16
0
0
0