LM3S600-IQN20-A0T Bookham Technology, Inc., LM3S600-IQN20-A0T Datasheet - Page 77

• Manufacturer Part Number: LM3S600-IQN20-A0T
• Description: Microcontroller
• Manufacturer: Bookham Technology, Inc.

Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0000.309F
October 01, 2007
Reset
Reset
Type
Type
Bit/Field
31:16
15:12
11:8
6:5
7
4
3
RO
RO
31
15
0
0
Register 15: Device Capabilities 1 (DC1), offset 0x010
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: PWM, ADC,
Watchdog timer, and debug capabilities. This register also indicates the maximum clock frequency
and maximum ADC sample rate. The format of this register is consistent with the RCGC0, SCGC0,
and DCGC0 clock control registers and the SRCR0 software reset control register.
RO
RO
30
14
MINSYSDIV
0
0
MINSYSDIV
reserved
reserved
reserved
Name
MPU
WDT
PLL
RO
RO
29
13
0
1
RO
RO
28
12
0
1
RO
RO
Type
27
11
0
0
RO
RO
RO
RO
RO
RO
RO
RO
RO
26
10
0
0
reserved
Reset
0x3
0
0
1
0
1
1
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MPU Present
When set, indicates that the Cortex-M3 Memory Protection Unit (MPU)
module is present. See the ARM Cortex-M3 Technical Reference Manual
for details on the MPU.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL Present
When set, indicates that the on-chip Phase Locked Loop (PLL) is
present.
Watchdog Timer Present
When set, indicates that a watchdog timer is present.
RO
RO
Value
0x3
24
0
8
0
reserved
Description
Specifies a 50-MHz CPU clock with a PLL divider of 4.
MPU
RO
RO
23
0
7
1
RO
RO
22
0
6
0
reserved
RO
RO
21
0
5
0
PLL
RO
RO
20
0
4
1
LM3S600 Microcontroller
WDT
RO
RO
19
0
3
1
SWO
RO
RO
18
0
2
1
SWD
RO
RO
17
0
1
1
JTAG
RO
RO
16
0
0
1
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