LM3S600-IQN20-A0T Bookham Technology, Inc., LM3S600-IQN20-A0T Datasheet - Page 164
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LM3S600-IQN20-A0T
Manufacturer Part Number
LM3S600-IQN20-A0T
Description
Microcontroller
Manufacturer
Bookham Technology, Inc.
Datasheet
1.LM3S600-IQN20-A0T.pdf
(378 pages)
- Current page: 164 of 378
- Download datasheet (4Mb)
General-Purpose Timers
9.3
9.3.1
164
Figure 9-4. 16-Bit PWM Mode Example
Initialization and Configuration
To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0,
TIMER1, and TIMER2 bits in the RCGC1 register.
This section shows module initialization and configuration examples for each of the supported timer
modes.
32-Bit One-Shot/Periodic Timer Mode
The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence:
1.
2.
3.
4.
5.
6.
Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making
any changes.
Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0.
Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR):
a.
b.
Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR).
If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
Write a value of 0x1 for One-Shot mode.
Write a value of 0x2 for Periodic mode.
Output
Signal
TnPWML = 0
TnPWML = 1
0xC350
0x411A
Count
TnEN set
GPTMTnR=GPTMnMR
Preliminary
GPTMTnR=GPTMnMR
October 01, 2007
Time
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