LM3S600-IQN20-A0T Bookham Technology, Inc., LM3S600-IQN20-A0T Datasheet - Page 122

• Manufacturer Part Number: LM3S600-IQN20-A0T
• Description: Microcontroller
• Manufacturer: Bookham Technology, Inc.

General-Purpose Input/Outputs (GPIOs)
8.1.3
8.1.4
8.1.5
8.2
Table 8-1. GPIO Pad Configuration Examples
122
Configuration
Digital Input (GPIO)
Digital Output (GPIO)
Open Drain Input
(GPIO)
Open Drain Output
(GPIO)
Open Drain
Input/Output (I
Digital Input (Timer
CCP)
Digital Output (Timer
PWM)
Digital Input/Output
(SSI)
Digital Input/Output
(UART)
2
When programming the following interrupt control registers, the interrupts should be masked (GPIOIM
set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can
generate a spurious interrupt if the corresponding bits are enabled.
Mode Control
The GPIO pins can be controlled by either hardware or software. When hardware control is enabled
via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 135), the pin state is
controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO
mode, where the GPIODATA register is used to read/write the corresponding pins.
Pad Control
The pad control registers allow for GPIO pad configuration by software based on the application
requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR,
GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers.
Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
Initialization and Configuration
To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the five JTAG pins) default to general-purpose inut mode
(GPIODIR=0 and GPIOAFSEL=0). Table 8-1 on page 122 shows all possible configurations of the
GPIO pads and the control register settings required to achieve them. Table 8-2 on page 123 shows
how a rising edge interrupt would be configured for pin 2 of a GPIO port.
C)
GPIO Register Bit Value
AFSEL
0
0
0
0
1
1
1
1
1
DIR
X
X
X
X
X
0
1
0
1
ODR
a
0
0
1
1
1
0
0
0
0
DEN
Preliminary
1
1
1
1
1
1
1
1
1
PUR
?
?
X
X
X
?
?
?
?
PDR
?
?
X
X
X
?
?
?
?
DR2R
X
X
X
?
?
?
?
?
?
DR4R
X
X
X
?
?
?
?
?
?
DR8R
October 01, 2007
X
X
X
?
?
?
?
?
?
SLR
X
X
X
?
?
?
?
?
?