LM3S600-IQN20-A0T Bookham Technology, Inc., LM3S600-IQN20-A0T Datasheet - Page 106

• Manufacturer Part Number: LM3S600-IQN20-A0T
• Description: Microcontroller
• Manufacturer: Bookham Technology, Inc.

Internal Memory
7.3
7.3.1
106
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Flash Memory Initialization and Configuration
This section shows examples for using the flash controller to perform various operations on the
contents of the flash memory.
Changing Flash Protection Bits
As discussed in “Flash Memory Protection” on page 104, changes to the protection bits must be
committed before they take effect. The sequence below is used change and commit a block protection
bit in the FMPRE or FMPPE registers. The sequence to change and commit a bit in software is as
follows:
1.
2.
3.
There is a special sequence to change and commit the DBG bits in the Flash Memory Protection
Read Enable (FMPRE) register. This sequence also sets and commits any changes from 1 to 0 in
the block protection bits (for execute-only) in the FMPRE register.
1.
2.
3.
Below is an example code sequence to permanently disable the JTAG and SWD interface to the
debug module using Luminary Micro's DriverLib peripheral driver library:
#include "hw_types.h"
#include "hw_flash.h"
void
permanently_disable_jtag_swd(void)
{
Loading the debug disable sequence into SRAM and running it once from SRAM after
programming the final end application code into flash
The Flash Memory Protection Read Enable (FMPRE) and Flash Memory Protection Program
Enable (FMPPE) registers are written, changing the intended bit(s). The action of these changes
can be tested by software while in this state.
The Flash Memory Address (FMA) register (see page 109) bit 0 is set to 1 if the FMPPE register
is to be committed; otherwise, a 0 commits the FMPRE register.
The Flash Memory Control (FMC) register (see page 111) is written with the COMT bit set. This
initiates a write sequence and commits the changes.
The Flash Memory Protection Read Enable (FMPRE) register is written, changing the intended
bit(s). The action of these changes can be tested by software while in this state.
The Flash Memory Address (FMA) register (see ppage 109) is written with a value of 0x900.
The Flash Memory Control (FMC) register (see page 111) is written with the COMT bit set. This
initiates a write sequence and commits the changes.
//
// Clear the DBG field of the FMPRE register. Note that the value
// used in this instance does not affect the state of the BlockN
// bits, but were the value different, all bits in the FMPRE are
// affected by this function!
//
HWREG(FLASH_FMPRE) &= 0x3fffffff;
//
// The following sequence activates the one-time
Preliminary
October 01, 2007