LM3S600-IQN20-A0T Bookham Technology, Inc., LM3S600-IQN20-A0T Datasheet - Page 277
![no-image](/images/no-image-200.jpg)
LM3S600-IQN20-A0T
Manufacturer Part Number
LM3S600-IQN20-A0T
Description
Microcontroller
Manufacturer
Bookham Technology, Inc.
Datasheet
1.LM3S600-IQN20-A0T.pdf
(378 pages)
- Current page: 277 of 378
- Download datasheet (4Mb)
SSI Masked Interrupt Status (SSIMIS)
SSI0 base: 0x4000.8000
Offset 0x01C
Type RO, reset 0x0000.0000
October 01, 2007
Reset
Reset
Type
Type
Bit/Field
31:4
3
2
1
0
RO
RO
31
15
0
0
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
RO
RO
30
14
0
0
reserved
RORMIS
RXMIS
TXMIS
RTMIS
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
Type
27
11
0
0
RO
RO
RO
RO
RO
RO
RO
26
10
0
0
reserved
Reset
0
0
0
0
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Transmit FIFO Masked Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
SSI Receive FIFO Masked Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
SSI Receive Time-Out Masked Interrupt Status
Indicates that the receive time-out has occurred, when set.
SSI Receive Overrun Masked Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
TXMIS
LM3S600 Microcontroller
RO
RO
19
0
3
0
RXMIS
RO
RO
18
0
2
0
RTMIS
RO
RO
17
0
1
0
RORMIS
RO
RO
16
0
0
0
277
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