LM3S600-IQN20-A0T Bookham Technology, Inc., LM3S600-IQN20-A0T Datasheet - Page 268

• Manufacturer Part Number: LM3S600-IQN20-A0T
• Description: Microcontroller
• Manufacturer: Bookham Technology, Inc.

Synchronous Serial Interface (SSI)
SSI Control 1 (SSICR1)
SSI0 base: 0x4000.8000
Offset 0x004
Type R/W, reset 0x0000.0000
268
Reset
Reset
Type
Type
Bit/Field
31:4
3
2
RO
RO
31
15
0
0
Register 2: SSI Control 1 (SSICR1), offset 0x004
SSICR1 is control register 1 and contains bit fields that control various functions within the SSI
module. Master and slave mode functionality is controlled by this register.
RO
RO
30
14
0
0
reserved
Name
SOD
MS
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
Type
27
11
R/W
R/W
0
0
RO
RO
RO
26
10
0
0
reserved
Reset
0x00
0
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Slave Mode Output Disable
This bit is relevant only in the Slave mode (MS=1). In multiple-slave
systems, it is possible for the SSI master to broadcast a message to all
slaves in the system while ensuring that only one slave drives data onto
the serial output line. In such systems, the TXD lines from multiple slaves
could be tied together. To operate in such a system, the SOD bit can be
configured so that the SSI slave does not drive the SSITx pin.
The SOD values are defined as follows:
SSI Master/Slave Select
This bit selects Master or Slave mode and can be modified only when
SSI is disabled (SSE=0).
The MS values are defined as follows:
RO
RO
Value
Value
24
0
8
0
reserved
0
1
0
1
Description
SSI can drive SSITx output in Slave Output mode.
SSI must not drive the SSITx output in Slave mode.
Description
Device configured as a master.
Device configured as a slave.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
SOD
R/W
RO
19
0
3
0
R/W
RO
MS
18
0
2
0
October 01, 2007
SSE
R/W
RO
17
0
1
0
LBM
R/W
RO
16
0
0
0