LM3S600-IQN20-A0T Bookham Technology, Inc., LM3S600-IQN20-A0T Datasheet - Page 14

• Manufacturer Part Number: LM3S600-IQN20-A0T
• Description: Microcontroller
• Manufacturer: Bookham Technology, Inc.

Table of Contents
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Inter-Integrated Circuit (I
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Analog Comparators ................................................................................................................... 326
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
14
SSI Status (SSISR), offset 0x00C ................................................................................... 271
SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 273
SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 274
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 276
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 277
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 278
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 279
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 280
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 281
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 282
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 283
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 284
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 285
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 286
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 287
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 288
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 289
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 290
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 332
Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 333
Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 334
Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 335
Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 336
Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 336
Analog Comparator Status 2 (ACSTAT2), offset 0x60 ....................................................... 336
Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 337
Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 337
Analog Comparator Control 2 (ACCTL2), offset 0x64 ...................................................... 337
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 305
C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 306
C Master Data (I2CMDR), offset 0x008 ......................................................................... 310
C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 311
C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 312
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 313
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 314
C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 315
C Master Configuration (I2CMCR), offset 0x020 ............................................................ 316
C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 318
C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 319
C Slave Data (I2CSDR), offset 0x008 ........................................................................... 321
C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 322
C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 323
C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 324
C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 325
2
C) Interface ........................................................................................ 291
Preliminary
October 01, 2007