LM3S600-IQN20-A0T Bookham Technology, Inc., LM3S600-IQN20-A0T Datasheet - Page 117

• Manufacturer Part Number: LM3S600-IQN20-A0T
• Description: Microcontroller
• Manufacturer: Bookham Technology, Inc.

Flash Memory Protection Read Enable (FMPRE)
Base 0x400F.E000
Offset 0x130
Type R/W, reset 0x8000.FFFF
October 01, 2007
Reset
Reset
Type
Type
Bit/Field
31:0
R/W
R/W
31
15
1
1
Register 8: Flash Memory Protection Read Enable (FMPRE), offset 0x130
Note:
This register stores the read-only protection bits for each 2-KB flash block (see the FMPPE registers
for the execute-only protection bits). This register is loaded during the power-on reset sequence.
The factory settingsare a value of 1 for all implemented banks. This implements a policy of open
access and programmability. The register bits may be changed by writing the specific register bit.
However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may
NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at
which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it
may be restored by executing a power-on reset sequence. For additional information, see the “Flash
Memory Protection” section.
R/W
R/W
30
14
0
1
READ_ENABLE
Name
Offset is relative to System Control base address of 0x400FE000.
R/W
R/W
29
13
0
1
R/W
R/W
28
12
0
1
R/W
R/W
Type
27
11
R/W
0
1
R/W
R/W
26
10
0
1
0x8000FFFF
Reset
R/W
R/W
25
0
9
1
Preliminary
READ_ENABLE
READ_ENABLE
Description
Flash Read Enable
Each bit position maps 2 Kbytes of Flash to be read-enabled.
R/W
R/W
Value
0x8000FFFF
24
0
8
1
R/W
R/W
23
0
7
1
Description
Enables 32 KB of flash.
R/W
R/W
22
0
6
1
R/W
R/W
21
0
5
1
R/W
R/W
20
0
4
1
LM3S600 Microcontroller
R/W
R/W
19
0
3
1
R/W
R/W
18
0
2
1
R/W
R/W
17
0
1
1
R/W
R/W
16
0
0
1
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