LM3S600-IQN20-A0T Bookham Technology, Inc., LM3S600-IQN20-A0T Datasheet - Page 7

• Manufacturer Part Number: LM3S600-IQN20-A0T
• Description: Microcontroller
• Manufacturer: Bookham Technology, Inc.

List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 7-1.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 10-1.
Figure 11-1.
Figure 11-2.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 12-4.
Figure 12-5.
Figure 12-6.
Figure 12-7.
Figure 12-8.
Figure 12-9.
Figure 12-10. MICROWIRE Frame Format (Single Frame) .................................................................... 262
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 263
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 263
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 13-4.
Figure 13-5.
Figure 13-6.
Figure 13-7.
Figure 13-8.
Figure 13-9.
Figure 13-10. Master Burst RECEIVE .................................................................................................. 299
Figure 13-11. Master Burst RECEIVE after Burst SEND ........................................................................ 300
Figure 13-12. Master Burst SEND after Burst RECEIVE ........................................................................ 301
October 01, 2007
Stellaris
CPU Block Diagram ......................................................................................................... 29
TPIU Block Diagram ........................................................................................................ 30
JTAG Module Block Diagram ............................................................................................ 39
Test Access Port State Machine ....................................................................................... 42
IDCODE Register Format ................................................................................................. 46
BYPASS Register Format ................................................................................................ 46
Boundary Scan Register Format ....................................................................................... 47
External Circuitry to Extend Reset .................................................................................... 49
Main Clock Tree .............................................................................................................. 52
Flash Block Diagram ...................................................................................................... 103
GPIO Port Block Diagram ............................................................................................... 120
GPIODATA Write Example ............................................................................................. 121
GPIODATA Read Example ............................................................................................. 121
GPTM Module Block Diagram ........................................................................................ 158
16-Bit Input Edge Count Mode Example .......................................................................... 162
16-Bit Input Edge Time Mode Example ........................................................................... 163
16-Bit PWM Mode Example ............................................................................................ 164
WDT Module Block Diagram .......................................................................................... 193
UART Module Block Diagram ......................................................................................... 217
UART Character Frame ................................................................................................. 218
SSI Module Block Diagram ............................................................................................. 254
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 256
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 257
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 258
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 258
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 259
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 260
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 260
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 261
I
I
START and STOP Conditions ......................................................................................... 292
Complete Data Transfer with a 7-Bit Address ................................................................... 293
R/S Bit in First Byte ........................................................................................................ 293
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 296
Master Single RECEIVE ................................................................................................. 297
Master Burst SEND ....................................................................................................... 298
2
2
C Block Diagram ......................................................................................................... 291
C Bus Configuration .................................................................................................... 292
®
600 Series High-Level Block Diagram ................................................................ 22
Preliminary
2
C Bus ............................................................... 293
LM3S600 Microcontroller
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