LM3S600-IQN20-A0T Bookham Technology, Inc., LM3S600-IQN20-A0T Datasheet - Page 53

• Manufacturer Part Number: LM3S600-IQN20-A0T
• Description: Microcontroller
• Manufacturer: Bookham Technology, Inc.

6.1.4.3
6.1.4.4
6.1.4.5
6.1.4.6
October 01, 2007
PLL Frequency Configuration
The PLL is disabled by default during power-on reset and is enabled later by software if required.
Software configures the PLL input reference clock source, specifies the output divisor to set the
system clock frequency, and enables the PLL to drive the output.
If the main oscillator provides the clock reference to the PLL, the translation provided by hardware
and used to program the PLL is available for software in the XTAL to PLL Translation (PLLCFG)
register (see page 70). The internal translation provides a translation within ± 1% of the targeted
PLL VCO frequency.
The XTAL bit in the RCC register (see page 66) describes the available crystal choices and default
programming of the PLLCFG register. The crystal number is written into the XTAL field of the
Run-Mode Clock Configuration (RCC) register. Any time the XTAL field changes, the new settings
are translated and the internal PLL settings are updated.
PLL Modes
The PLL has two modes of operation: Normal and Power-Down
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■
The modes are programmed using the RCC register fields (see page 66).
PLL Operation
If the PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is T
18-6 on page 350). During this time, the PLL is not usable as a clock reference.
The PLL is changed by one of the following:
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■
A counter is defined to measure the T
oscillator. The range of the main oscillator has been taken into account and the down counter is set
to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). Hardware is provided to keep
the PLL from being used as a system clock until the T
changes above. It is the user's responsibility to have a stable clock source (like the main oscillator)
before the RCC register is switched to use the PLL.
Clock Verification Timers
There are three identical clock verification circuits that can be enabled though software. The circuit
checks the faster clock by a slower clock using timers:
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■
■
If the verification timer function is enabled and a failure is detected, the main clock tree is immediately
switched to a working clock and an interrupt is generated to the controller. Software can then
Normal: The PLL multiplies the input clock reference and drives the output.
Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
Change in the PLL from Power-Down to Normal mode.
The main oscillator checks the PLL.
The main oscillator checks the internal oscillator.
The internal oscillator divided by 64 checks the main oscillator.
Preliminary
READY
requirement. The counter is clocked by the main
READY
condition is met after one of the two
LM3S600 Microcontroller
READY
(see Table
53