LM3S600-IQN20-A0T Bookham Technology, Inc., LM3S600-IQN20-A0T Datasheet - Page 114
![no-image](/images/no-image-200.jpg)
LM3S600-IQN20-A0T
Manufacturer Part Number
LM3S600-IQN20-A0T
Description
Microcontroller
Manufacturer
Bookham Technology, Inc.
Datasheet
1.LM3S600-IQN20-A0T.pdf
(378 pages)
- Current page: 114 of 378
- Download datasheet (4Mb)
Internal Memory
Flash Controller Interrupt Mask (FCIM)
Base 0x400F.D000
Offset 0x010
Type R/W, reset 0x0000.0000
114
Reset
Reset
Type
Type
Bit/Field
31:2
1
0
RO
RO
31
15
0
0
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010
This register controls whether the flash controller generates interrupts to the controller.
RO
RO
30
14
0
0
reserved
PMASK
AMASK
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
Type
27
11
R/W
R/W
0
0
RO
RO
RO
26
10
0
0
Reset
0x00
0
0
RO
RO
25
0
9
0
reserved
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Programming Interrupt Mask
This bit controls the reporting of the programming raw interrupt status
to the controller. If set, a programming-generated interrupt is promoted
to the controller. Otherwise, interrupts are recorded but suppressed from
the controller.
Access Interrupt Mask
This bit controls the reporting of the access raw interrupt status to the
controller. If set, an access-generated interrupt is promoted to the
controller. Otherwise, interrupts are recorded but suppressed from the
controller.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
RO
RO
18
0
2
0
October 01, 2007
PMASK
R/W
RO
17
0
1
0
AMASK
R/W
RO
16
0
0
0
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